High Speed and Independent Carry Chain Carry Look Ahead Adder (cla) Implementation Using Cadence-eda
نویسنده
چکیده
In this paper focuses on carry -look ahead adders have done research on the design of high-speed, low-area, or low-power adders. Addition is the fundamental operation for any VLSI processors or digital signal processing. The main objective of this paper is to reduce the propagation delay and gate count of the Carry look-Ahead Adder (CLA).Which will also reflect in the reduction of area and power of the adder module. Experimental results reveal that the proposed adders achieve delay, power and area reductions for Multi bit addition. We know that in adder circuits propagation delay is the main drawback. To overcome this drawback the independent carry technique is introduced. Here in this paper 4, 8, 16-bit adders are been designed and the gate count, power and delay are measured using CADENCE EDA, and then compared with the conventional adder.
منابع مشابه
Performance Analysis of Different Bit Carry Look Ahead Adder Using VHDL Environment
Adders are some of the most critical data path circuits requiring considerable design effort in order to squeeze out as much performance gain as possible. Various adder structures can be used to execute addition such as serial and parallel structures and most of researches have done research on the design of high-speed, low-area, or lowpower adders. Adders like ripple carry adder, carry select ...
متن کاملHigh Speed-Low Power Radix-8 Booth Decoded Multiplier
This paper proposed a new method for adding sum and carry using carry look-ahead adder at the final stage of the radix-8 booth decoding multiplier. In a conventional radix-8 booth decoded multiplier, full adders and half adders are used to add sum and carry. After partial product reduction using booth decoding, the partial product rows are required to add for final result. In this method carry ...
متن کاملPerformance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder
In this paper, design of two different array multipliers are presented, one by using carry-look-ahead (CLA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison ...
متن کاملHigh Performance and Low Power 8 bit 16T full adder using MTCMOS Technique
The most fundamental operation of any processor is the addition. For any circuit there are two important parameters that comes into count is high speed and low power consumption. Hence the speed of various modules should be maximized to dominate overall performance. Depending upon these parameters various adders can be invented like Carry Look Ahead Adder(CLA),Carry Skip Adder(CSA) and Ripple C...
متن کاملAn area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit
This paper presents a highly area-efficient CMOS carry-select adder (CSA) with a regular and iterative-shared transistor structure very suitable for implementation in VLSI. This adder is based on both a static and compact multi-output carry look-ahead (CLA) circuit and a very simple select circuit. Comparisons with other representative 32-bit CSAs show that the proposed adder reduces the area b...
متن کامل